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Stefan Lohmaier d5cfec9e42 feat(i18n): dev-process repo in English

- README.md: full English rewrite
- All 13 vorlagen MD templates hand-translated:
  PID, PM-Plan, QA-Plan, SWE-Plan, Test-Plan,
  SA, SWA, Review-Protokoll, Non-Conformity,
  MISRA-Deviation-Permit, MISRA-Deviation-Record,
  Traceability-Matrix, angebot (quotation)
- Master Word template (slohmaier-doc-template.docx) regenerated
  in English: cover page, document control, TOC headers,
  classification banner all English
- All derived Word vorlagen regenerated from English MD sources

Still to translate: toolstack.md, gitea-aspice-setup.md

2026-05-12 03:42:35 -07:00

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1.0

SWE-XXX

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SWA-XXX: [Component name]

Software Architectural Design Element (ASPICE SWE.2). Describes a software component and its mapping to software requirements.

Field	Value
Project	[Project name]
Date	[YYYY-MM-DD]
Version	[1.0]
Status	[Draft / Released]
ASIL	[QM / A / B / C / D]
Author	[Name]
Parent	[SA-XXX, if applicable]

1. Responsibility

[One or two sentences: what does this component do? Where is the boundary to neighbouring components?]

2. Static view

2.1 Component diagram

@startuml
package "[Component name]" {
  [Submodule A]
  [Submodule B]
}
[Submodule A] --> [Submodule B]
[Component name] ..> [Neighbour component] : uses
@enduml

2.2 Embedded / used components

Component	Reference	Use
[Name]	SWA-YYY	[for what]

3. Interfaces

3.1 Provided interface

/**
 * @brief [Short description]
 * @param [name] [Meaning, value range]
 * @return [Status / value]
 * @pre   [Precondition]
 * @post  [Postcondition]
 */
Status component_init(const Config* cfg);

Function	Purpose	Pre-condition	Post-condition
component_init	Initialisation	cfg != NULL	Component ready
component_send	Send data	initialised	Data in TX buffer

3.2 Required interface

Interface	Provided by	Purpose
ILogger::log()	LoggerComponent	Diagnostics / tracing
IClock::now()	ClockComponent	Timestamps

4. Dynamic behaviour

4.1 Sequence diagram (critical flow)

@startuml
participant App
participant "[Component]" as C
participant HW
App -> C: init(cfg)
C -> HW: configure
HW --> C: ok
C --> App: STATUS_OK
@enduml

4.2 State diagram (if applicable)

@startuml
[*] --> Uninitialized
Uninitialized --> Ready : init()
Ready --> Busy : send()
Busy --> Ready : tx_done
Ready --> Error : fault
Error --> Ready : reset()
@enduml

5. Resource demand

Resource	Worst case	Method of determination
Stack	[e.g. 256 B]	[Measurement / static analysis]
Heap	[e.g. 0 B]	[No heap use]
Flash	[e.g. 4 KB]	[Linker map file]
RAM (static)	[e.g. 128 B]	[Linker map file]
CPU load	[e.g. < 1%]	[Measurement on target]
Worst-case timing	[e.g. 200 us / call init()]	[HiL measurement]

6. Failure behaviour

Failure case	Detection	Reaction
Invalid config	Parameter check	Status STATUS_EINVAL
HW timeout	Timer	Retry, then STATUS_TIMEOUT
Buffer full	Pre-write check	STATUS_NOSPACE

7. Design decisions

Decision	Alternative(s)	Rationale
[e.g. static allocation]	[Heap]	[Deterministic, MISRA]
[Locking strategy]	[Mutex / lock-free]	[Rationale]

8. Mapping to requirements

Requirement	How covered	Verification test
SWE-XXX	[which part of this component fulfils it]	TST-UNIT-XXX, TST-INT-YYY
SWE-YYY	[...]	TST-UNIT-YYY

Every SWE requirement listed in links must have an entry in this table.

9. Detailed design

Detailed design (ASPICE SWE.3) is maintained separately under arch/swd/SWD-XXX.md from ASIL-C upwards. For ASIL-A/B and QM, code plus header comments are sufficient.

Changes to this architecture element go through a PR with at least 2 technical-review approvals (see SWE Plan).

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