Stefan Lohmaier
247b8311f3
Final German naming cleanup in dev-process: - vorlagen/ -> templates/ - vorlagen-word/ -> templates-word/ - tools/generate_word_vorlagen.sh -> tools/generate_word_templates.sh - *-vorlage.md / *-vorlage.docx -> *-template.md / *-template.docx - Review-Protokoll-vorlage.* -> Review-Minutes-template.* - angebot-vorlage.* -> quote-template.* - angebot-beispiel.html -> quote-example.html All references in README.md, toolstack/toolstack.md, build_word_template.py, and generate_word_templates.sh updated. The master Word style template (slohmaier-doc-template.docx) was already English-named. The dev-process repo is now fully English in both content and structure.
148 lines
4.6 KiB
Markdown
148 lines
4.6 KiB
Markdown
---
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active: true
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level: 1.0
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links:
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- SWE-XXX: [hash]
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---
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# SWA-XXX: [Component name]
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> **Software Architectural Design Element (ASPICE SWE.2).**
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> Describes a software component and its mapping to software requirements.
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| Field | Value |
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|----------|--------------------------------|
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| Project | [Project name] |
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| Date | [YYYY-MM-DD] |
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| Version | [1.0] |
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| Status | [Draft / Released] |
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| ASIL | [QM / A / B / C / D] |
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| Author | [Name] |
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| Parent | [SA-XXX, if applicable] |
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---
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## 1. Responsibility
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[One or two sentences: what does this component do? Where is the boundary to neighbouring components?]
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## 2. Static view
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### 2.1 Component diagram
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```plantuml
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@startuml
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package "[Component name]" {
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[Submodule A]
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[Submodule B]
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}
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[Submodule A] --> [Submodule B]
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[Component name] ..> [Neighbour component] : uses
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@enduml
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```
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### 2.2 Embedded / used components
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| Component | Reference | Use |
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|---------------|-----------|---------------------------|
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| [Name] | SWA-YYY | [for what] |
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## 3. Interfaces
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### 3.1 Provided interface
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```c
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/**
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* @brief [Short description]
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* @param [name] [Meaning, value range]
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* @return [Status / value]
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* @pre [Precondition]
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* @post [Postcondition]
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*/
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Status component_init(const Config* cfg);
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```
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| Function | Purpose | Pre-condition | Post-condition |
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|------------------|--------------------|-----------------------|------------------------|
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| component_init | Initialisation | cfg != NULL | Component ready |
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| component_send | Send data | initialised | Data in TX buffer |
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### 3.2 Required interface
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| Interface | Provided by | Purpose |
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|-------------------|--------------------|---------------------|
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| ILogger::log() | LoggerComponent | Diagnostics / tracing |
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| IClock::now() | ClockComponent | Timestamps |
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## 4. Dynamic behaviour
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### 4.1 Sequence diagram (critical flow)
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```plantuml
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@startuml
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participant App
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participant "[Component]" as C
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participant HW
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App -> C: init(cfg)
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C -> HW: configure
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HW --> C: ok
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C --> App: STATUS_OK
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@enduml
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```
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### 4.2 State diagram (if applicable)
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```plantuml
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@startuml
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[*] --> Uninitialized
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Uninitialized --> Ready : init()
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Ready --> Busy : send()
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Busy --> Ready : tx_done
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Ready --> Error : fault
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Error --> Ready : reset()
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@enduml
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```
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## 5. Resource demand
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| Resource | Worst case | Method of determination |
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|-------------------|--------------|------------------------------|
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| Stack | [e.g. 256 B] | [Measurement / static analysis] |
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| Heap | [e.g. 0 B] | [No heap use] |
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| Flash | [e.g. 4 KB] | [Linker map file] |
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| RAM (static) | [e.g. 128 B] | [Linker map file] |
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| CPU load | [e.g. < 1%] | [Measurement on target] |
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| Worst-case timing | [e.g. 200 us / call init()] | [HiL measurement] |
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## 6. Failure behaviour
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| Failure case | Detection | Reaction |
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|-----------------------|-------------------|---------------------------|
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| Invalid config | Parameter check | Status STATUS_EINVAL |
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| HW timeout | Timer | Retry, then STATUS_TIMEOUT |
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| Buffer full | Pre-write check | STATUS_NOSPACE |
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## 7. Design decisions
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| Decision | Alternative(s) | Rationale |
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|------------------------|------------------|----------------------------|
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| [e.g. static allocation] | [Heap] | [Deterministic, MISRA] |
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| [Locking strategy] | [Mutex / lock-free] | [Rationale] |
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## 8. Mapping to requirements
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| Requirement | How covered | Verification test |
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|---------------|-----------------------------------------------|----------------------------|
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| SWE-XXX | [which part of this component fulfils it] | TST-UNIT-XXX, TST-INT-YYY |
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| SWE-YYY | [...] | TST-UNIT-YYY |
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Every SWE requirement listed in `links` must have an entry in this table.
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## 9. Detailed design
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Detailed design (ASPICE SWE.3) is maintained separately under `arch/swd/SWD-XXX.md` from ASIL-C upwards. For ASIL-A/B and QM, code plus header comments are sufficient.
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---
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*Changes to this architecture element go through a PR with at least 2 technical-review approvals (see SWE Plan).*
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