feat(i18n): dev-process repo in English
- README.md: full English rewrite - All 13 vorlagen MD templates hand-translated: PID, PM-Plan, QA-Plan, SWE-Plan, Test-Plan, SA, SWA, Review-Protokoll, Non-Conformity, MISRA-Deviation-Permit, MISRA-Deviation-Record, Traceability-Matrix, angebot (quotation) - Master Word template (slohmaier-doc-template.docx) regenerated in English: cover page, document control, TOC headers, classification banner all English - All derived Word vorlagen regenerated from English MD sources Still to translate: toolstack.md, gitea-aspice-setup.md
This commit is contained in:
Stefan Lohmaier
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-72
@@ -5,83 +5,83 @@ links:
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- SWE-XXX: [hash]
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---
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# SWA-XXX: [Komponenten-Name]
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# SWA-XXX: [Component name]
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> **Software Architectural Design Element (ASPICE SWE.2).**
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> Beschreibt eine Software-Komponente und ihr Mapping auf Software-Anforderungen.
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> Describes a software component and its mapping to software requirements.
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| Feld | Wert |
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|----------|-------------------------------|
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| Projekt | [Projektname] |
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| Datum | [YYYY-MM-DD] |
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| Version | [1.0] |
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| Status | [Entwurf / Freigegeben] |
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| ASIL | [QM / A / B / C / D] |
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| Autor | [Name] |
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| Parent | [SA-XXX, falls vorhanden] |
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| Field | Value |
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|----------|--------------------------------|
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| Project | [Project name] |
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| Date | [YYYY-MM-DD] |
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| Version | [1.0] |
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| Status | [Draft / Released] |
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| ASIL | [QM / A / B / C / D] |
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| Author | [Name] |
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| Parent | [SA-XXX, if applicable] |
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---
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## 1. Verantwortung
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## 1. Responsibility
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[Ein bis zwei Saetze: Was tut diese Komponente? Wo ist die Abgrenzung zu Nachbar-Komponenten?]
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[One or two sentences: what does this component do? Where is the boundary to neighbouring components?]
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## 2. Statische Sicht
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## 2. Static view
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### 2.1 Komponentendiagramm
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### 2.1 Component diagram
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```plantuml
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@startuml
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package "[Komponenten-Name]" {
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[Submodul A]
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[Submodul B]
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package "[Component name]" {
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[Submodule A]
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[Submodule B]
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}
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[Submodul A] --> [Submodul B]
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[Komponenten-Name] ..> [Nachbar-Komponente] : nutzt
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[Submodule A] --> [Submodule B]
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[Component name] ..> [Neighbour component] : uses
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@enduml
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```
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### 2.2 Eingebettete / verwendete Komponenten
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### 2.2 Embedded / used components
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| Komponente | Verweis | Verwendung |
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|---------------|----------|--------------------------|
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| [Name] | SWA-YYY | [wofuer] |
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| Component | Reference | Use |
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|---------------|-----------|---------------------------|
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| [Name] | SWA-YYY | [for what] |
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## 3. Schnittstellen
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## 3. Interfaces
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### 3.1 Bereitgestellte Schnittstelle (Provided)
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### 3.1 Provided interface
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```c
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/**
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* @brief [Kurzbeschreibung]
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* @param [name] [Bedeutung, Wertebereich]
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* @return [Status / Wert]
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* @pre [Vorbedingung]
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* @post [Nachbedingung]
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* @brief [Short description]
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* @param [name] [Meaning, value range]
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* @return [Status / value]
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* @pre [Precondition]
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* @post [Postcondition]
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*/
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Status component_init(const Config* cfg);
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```
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| Funktion | Zweck | Pre-Condition | Post-Condition |
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|------------------|----------------------|-----------------------|------------------------|
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| component_init | Initialisierung | cfg != NULL | Komponente betriebsbereit |
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| component_send | Daten senden | initialisiert | Daten in TX-Buffer |
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| Function | Purpose | Pre-condition | Post-condition |
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|------------------|--------------------|-----------------------|------------------------|
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| component_init | Initialisation | cfg != NULL | Component ready |
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| component_send | Send data | initialised | Data in TX buffer |
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### 3.2 Benoetigte Schnittstelle (Required)
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### 3.2 Required interface
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| Schnittstelle | Bereitgestellt von | Zweck |
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|-------------------|--------------------|-----------------------|
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| ILogger::log() | LoggerComponent | Diagnose / Tracing |
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| IClock::now() | ClockComponent | Zeitstempel |
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| Interface | Provided by | Purpose |
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|-------------------|--------------------|---------------------|
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| ILogger::log() | LoggerComponent | Diagnostics / tracing |
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| IClock::now() | ClockComponent | Timestamps |
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## 4. Dynamisches Verhalten
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## 4. Dynamic behaviour
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### 4.1 Sequenzdiagramm (kritischer Ablauf)
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### 4.1 Sequence diagram (critical flow)
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```plantuml
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@startuml
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participant App
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participant "[Komponente]" as C
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participant "[Component]" as C
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participant HW
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App -> C: init(cfg)
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C -> HW: configure
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@@ -90,7 +90,7 @@ C --> App: STATUS_OK
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@enduml
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```
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### 4.2 Zustandsdiagramm (falls zutreffend)
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### 4.2 State diagram (if applicable)
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```plantuml
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@startuml
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@@ -103,46 +103,45 @@ Error --> Ready : reset()
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@enduml
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```
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## 5. Ressourcen-Bedarf
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## 5. Resource demand
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| Ressource | Worst-Case | Methode der Bestimmung |
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|-------------------|--------------|-----------------------------|
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| Stack | [z.B. 256 B] | [Messung / statische Analyse] |
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| Heap | [z.B. 0 B] | [keine Heap-Nutzung] |
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| Flash | [z.B. 4 KB] | [Map-File des Linkers] |
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| RAM (statisch) | [z.B. 128 B] | [Map-File des Linkers] |
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| CPU-Last | [z.B. < 1 %] | [Messung auf Zielsystem] |
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| Worst-Case Timing | [z.B. 200 us / Aufruf init()] | [Messung HiL] |
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| Resource | Worst case | Method of determination |
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|-------------------|--------------|------------------------------|
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| Stack | [e.g. 256 B] | [Measurement / static analysis] |
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| Heap | [e.g. 0 B] | [No heap use] |
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| Flash | [e.g. 4 KB] | [Linker map file] |
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| RAM (static) | [e.g. 128 B] | [Linker map file] |
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| CPU load | [e.g. < 1%] | [Measurement on target] |
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| Worst-case timing | [e.g. 200 us / call init()] | [HiL measurement] |
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## 6. Fehlerverhalten
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## 6. Failure behaviour
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| Fehlerfall | Erkennung | Reaktion |
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| Failure case | Detection | Reaction |
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|-----------------------|-------------------|---------------------------|
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| Ungueltige Konfig | Parameter-Check | Status STATUS_EINVAL |
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| HW-Timeout | Timer | Retry, dann STATUS_TIMEOUT |
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| Buffer voll | Check vor Schreiben | STATUS_NOSPACE |
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| Invalid config | Parameter check | Status STATUS_EINVAL |
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| HW timeout | Timer | Retry, then STATUS_TIMEOUT |
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| Buffer full | Pre-write check | STATUS_NOSPACE |
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## 7. Designentscheidungen
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## 7. Design decisions
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| Entscheidung | Alternative(n) | Begruendung |
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|------------------------|------------------|--------------------------|
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| [z.B. statische Allokation] | [Heap] | [deterministisch, MISRA] |
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| [Lock-Strategie] | [Mutex / lock-free] | [Begruendung] |
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| Decision | Alternative(s) | Rationale |
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|------------------------|------------------|----------------------------|
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| [e.g. static allocation] | [Heap] | [Deterministic, MISRA] |
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| [Locking strategy] | [Mutex / lock-free] | [Rationale] |
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## 8. Mapping auf Anforderungen
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## 8. Mapping to requirements
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| Anforderung | Wie abgedeckt | Verifikations-Test |
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|---------------|----------------------------------------------|----------------------------|
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| SWE-XXX | [welcher Teil dieser Komponente erfuellt es] | TST-UNIT-XXX, TST-INT-YYY |
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| Requirement | How covered | Verification test |
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|---------------|-----------------------------------------------|----------------------------|
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| SWE-XXX | [which part of this component fulfils it] | TST-UNIT-XXX, TST-INT-YYY |
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| SWE-YYY | [...] | TST-UNIT-YYY |
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Jede in den `links` referenzierte SWE-Anforderung muss in dieser Tabelle einen Eintrag haben.
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Every SWE requirement listed in `links` must have an entry in this table.
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## 9. Detail-Design
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## 9. Detailed design
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Detail-Design (ASPICE SWE.3) wird ab ASIL-C separat in `arch/swd/SWD-XXX.md` gefuehrt.
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Fuer ASIL-A/B und QM ist Code + Header-Kommentare ausreichend.
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Detailed design (ASPICE SWE.3) is maintained separately under `arch/swd/SWD-XXX.md` from ASIL-C upwards. For ASIL-A/B and QM, code plus header comments are sufficient.
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---
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*Aenderungen an diesem Architektur-Element gehen per PR mit mind. 2 Technical-Review-Approvals (siehe SWE-Plan).*
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*Changes to this architecture element go through a PR with at least 2 technical-review approvals (see SWE Plan).*
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